Intel Quartus로 Verilog Timing Analysis

module cla32(a, b, ci, s, co);	//32-bit Carry Look-Ahead Adder
	input [31:0] a, b;	//operand
	input ci;				//carry in
	output [31:0] s;		//sum
	output co;				//carry out
	wire w0, w1, w2, w3, w4, w5, w6, w7;
	
	clb4 U0_clb4(a[3:0], b[3:0], ci, s[3:0], w0);
	clb4 U1_clb4(a[7:4], b[7:4], w0, s[7:4], w1);
	clb4 U2_clb4(a[11:8], b[11:8], w1, s[11:8], w2);
	clb4 U3_clb4(a[15:12], b[15:12], w2, s[15:12], w3);
	clb4 U4_clb4(a[19:16], b[19:16], w3, s[19:16], w4);
	clb4 U5_clb4(a[23:20], b[23:20], w4, s[23:20], w5);
	clb4 U6_clb4(a[27:24], b[27:24], w5, s[27:24], w6);
	clb4 U7_clb4(a[31:28], b[31:28], w6, s[31:28], co);
endmodule

module fa(a, b, ci, s, co);	//full adder
	input a, b;		//operand
	input ci;		//carry in
	output s;		//sum
	output co;		//carry out
	wire w0, w1, w2;

	assign s=a^b^ci;
	assign co=a&b|a&ci|b&ci;
endmodule

module rca4(a, b, ci, s, co);	//4-bit Ripple Carry Adder
	input [3:0] a, b;	//operand
	input ci;			//carry in
	output [3:0] s;	//sum
	output co;			//carry out
	wire w0, w1, w2;
	
	fa U0_fa(a[0], b[0], ci, s[0], w0);
	fa U1_fa(a[1], b[1], w0, s[1], w1);
	fa U2_fa(a[2], b[2], w1, s[2], w2);
	fa U3_fa(a[3], b[3], w2, s[3], co);
endmodule

module carry4(a, b, ci, co);	//4-bit Carry Look-Ahead Carry
	input [3:0] a, b;	//operand
	input ci;			//carry in
	output co;			//carry out
	wire [3:0] g, p;
	
	assign g=a&b;
	assign p=a|b;
	
	assign co=g[3]|p[3]&(g[2]|p[2]&(g[1]|p[1]&g[0]))|p[3]&p[2]&p[1]&p[0]&ci;
endmodule

module clb4(a, b, ci, s, co);	//4-bit Carry Look-Ahead Block
	input [3:0] a, b;
	input ci;
	output [3:0] s;
	output co;
	
	rca4 U0_rca4(a, b, ci, s,);
	carry4 U1_carry4(a, b, ci, co);	
endmodule

module reg32(clk, reset_n, d, q);
	input clk, reset_n;
	input [31:0] d;
	output reg [31:0] q;
	
	always @ (posedge clk or negedge reset_n)
	begin
		if(reset_n==0)	q<=0;
		else	q<=d;
	end
endmodule

module _dff_r(clk, reset_n, d, q);
	input clk, reset_n, d;
	output reg q;
	
	always @ (posedge clk or negedge reset_n)
	begin
		if(reset_n==0)	q<=0;
		else	q<=d;
	end
endmodule
 

module cla32_clk(clk, reset_n, a, b, ci, s, co);
	input clk, reset_n;
	input [31:0] a, b;	//operand
	input ci;				//carry in
	output [31:0] s;		//sum
	output co;				//carry out
	wire [31:0] w_a, w_b;	//outputs of registers
	wire w_ci;              //output of D Flip-flop
	wire [31:0] w_s;		//input of register
	wire w_co;              //input of D Flip-flop
	
	//input registers
	reg32 U0_reg32(clk, reset_n, a, w_a);
	reg32 U1_reg32(clk, reset_n, b, w_b);
	_dff_r U2_dff_r(clk, reset_n, ci, w_ci);
	
	//output registers
	reg32 U3_reg32(clk, reset_n, w_s, s);
	_dff_r U4_dff_r(clk, reset_n, w_co, co);
	
	//combinational circuit
	cla32 U5_cla32(w_a, w_b, w_ci, w_s, w_co);
endmodule